Die thickness of common, high-volume chip stacks range from 50 to 100 um while thinning industry aims for ultra-thin chips of 10 um thickness, or less. For the first time, the required interconnect length between vertically arranged adjacent chip layers has reached dimensions that can be reasonably realized by anisotropic conductive adhesives layers (ACA).

The reviews are in--and we're not talking about the latest summer blockbuster. Just one month after acquiring SMT Magazine, I-Connect007 published its first issue of the magazine. The feedback from loyal SMT readers has been overwhelmingly positive. SMT Magazine is just one example of what we have planned for the future.

DKN Research is now offering a Fine Silver Conductor Trial Kit capable of producing fine lines down to 50 microns to companies interested in producing high density thick film circuits.

Driven by strong IC market expansion and growth in emerging markets, SEMICON Taiwan 2010 returns to the Taipei World Trade Center September 8-10, 2010 with eight technology theme pavilions focusing on LEDs, MEMS, 3-D ICs and Advanced Packaging/Testing, Green Management, Compound Semiconductors, CMP, AOI and the Secondary Market for capital equipment.

University of Illinois engineers have developed a novel direct-writing method for manufacturing metal interconnects that could shrink integrated circuits and expand microelectronics.

EV Group has launched the EVG560HBL wafer bonder -- the industry's first fully automated wafer bonding system for high-brightness light emitting diode (HB-LED) manufacturing.

With the Applied Producer Avila system, Applied Materials becomes the first equipment supplier to offer comprehensive TSV solutions for speeding the development and time to market of 3D-ICs.

Alchimer S.A., a provider of nanometric deposition technology for through-silicon vias (TSV), semiconductor interconnects, and other electronic applications, announced today that Panasonic Corporation has become an equity investor in the company.

Advanced Electronic Packaging industry has grown to a position where its technology has outpaced the semiconductor technology, the parent industry it addresses.

Alchimer S.A. today announced a ground-breaking advance for filling narrow, high-aspect-ratio TSVs while significantly reducing the need for chemical components in the metallization process.

Die thickness of common, high-volume chip stacks range from 50 to 100 um while thinning industry aims for ultra-thin chips of 10 um thickness, or less. For the first time, the required interconnect length between vertically arranged adjacent chip layers has reached dimensions that can be reasonably realized by anisotropic conductive adhesives layers (ACA).

Demands for higher performance, multifunctionality and size reduction require package substrates to offer improved high-speed signal transmission, higher wiring density and high system reliability. An SAP is widely used with build-up dielectric materials to form the circuit features. Features of such metallization processes are detailed here.

Current demands require semiconductor package substrates to provide improved high-speed signal transmission capability, higher interconnect wiring density and high system reliability. An SAP is widely used with build-up dielectric materials to form the circuit features. This article describes the features of metallization processes for such applications.

Minsu (Tim) Lee Ph.D., Senior Researcher at Doosan Electro-Materials, discusses his company's long history with halogen-free materials. Doosan provides highly-reliable and environmentally-friendly substrate material for IC packages.

I-Connect007's team of editors, guest editors, videographers and video editors worked throughout the show to capture the keynotes, the industry's top technologists and business leaders, bringing our readers and viewers the world's most comprehensive event coverage and content.

Demands for higher performance, multifunctionality and size reduction require package substrates to offer improved high-speed signal transmission, higher wiring density and high system reliability. An SAP is widely used with build-up dielectric materials to form the circuit features. Features of such metallization processes are detailed here.

Current demands require semiconductor package substrates to provide improved high-speed signal transmission capability, higher interconnect wiring density and high system reliability. An SAP is widely used with build-up dielectric materials to form the circuit features. This article describes the features of metallization processes for such applications.

Minsu (Tim) Lee Ph.D., Senior Researcher at Doosan Electro-Materials, discusses his company's long history with halogen-free materials. Doosan provides highly-reliable and environmentally-friendly substrate material for IC packages.

Demands for higher performance, multifunctionality and size reduction require package substrates to offer improved high-speed signal transmission, higher wiring density and high system reliability. An SAP is widely used with build-up dielectric materials to form the circuit features. Features of such metallization processes are detailed here.

Current demands require semiconductor package substrates to provide improved high-speed signal transmission capability, higher interconnect wiring density and high system reliability. An SAP is widely used with build-up dielectric materials to form the circuit features. This article describes the features of metallization processes for such applications.