Note: An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate is supporting a solder bumped flip chip in a chip scale package (CSP) soldered on a PCB is presented in this paper.

Introduction

By IPC's definition, holes 6 mils (0.15 mm) or less in size on PCBs are called micro-vias. Many advantages to micro-via exist--much smaller pads can be used, saving on board size and weight; more chips can be placed in less space or on a smaller PCB, resulting in lower cost; and electrical performance, because capacitance is increased due to the smaller via length and diameter, and the inductance is reduced due to the shorter pathway created by the microvia compared to the plated through-hole (PTH). Combining microvia with via-in-pad (µVIP) saves even more PCB real estate.

In this study, the design, analysis and modeling of a VIP substrate for housing a solder bumped flip chip in a CSP15 soldered on a PCB are presented. Because of the special design, the substrate consists of a single core of organic material and two-metal layers of copper, and is manufactured with the conventional PCB process at a very low cost. Furthermore, the vias are laser drilled, thus, very small hole-size (0.15 mm to 0.1 mm) can be achieved.

The proposed substrate is used to support a functional 32-pin, low-power, high-speed static random access memory (SRAM). The assembled solder bumped flip chip in micro-VIP CSP package is soldered on a PCB. Time-temperature-dependent finite element method is used to perform the thermal stress and strain analysis.

The Structure 32-pin SRAM IC Chip

In this section the chip, µVIP substrate, solder bumped flip chip on µVIP substrate CSP and µVIP CSP on PCB will be discussed.



























Figure 1a and 1b: The functional 32-pin SRAM.

The functional 32-pin SRAM (Figures 1a and 1b), is designed and manufactured at very high yield and low cost by United Microelectronics Corporation (UMC) on an 8" wafer. The major function of this SRAM chip is for very high speed and low power applications. The major characteristics of the chip for designing the Cu µVIP are listed as follows:

• Chip sizes are 5.334 mm x 3.662 mm;
• Pad sizes are 0.075 mm x 0.075 mm;
• Pad pitch is 0.195 mm (minimum);
• Chip thickness is 0.675 mm;
• Chip pads are distributed on two shorter sides; and
• Two pads for ground and two pads for power.