The 46th Design Automation Conference (DAC), to be held on July 26-31, 2009 at the Moscone Center in San Francisco, California, will offer six educational, full-day tutorials focused on a variety of design methods. The full-day tutorials will be held Monday, July 27 and Friday, July 31, and will provide CAD professionals, design engineers, their management, as well as academic researchers with an in-depth look at some of the most challenging and topical areas of electronic design, as industry professionals and experts address key trends and issues facing today's EDA industry. This year, tutorial attendees have the opportunity to earn university Continuing Education Credits in the field of VLSI and Design Automation through new partnerships between DAC and the University of California Santa Cruz (UCSC) Extension and the University of California San Diego (UCSD) Extension.

"The full-day tutorials are an important part of DAC that offer participants the opportunity to explore a subject in-depth and gain valuable, practical knowledge," said Dennis Sylvester, 46th DAC Tutorial Chair. "This year we're excited to partner with two UC campuses to offer tutorial participants the opportunity to earn university credit for their work."

Full-Day Tutorials
Low-Power SOC Design: State of the Art and Directions
Monday, July 27: 8:30 a.m. - 4:30 p.m.

This tutorial will focus on industrial case studies that highlight state-of-the-art techniques to achieve improved energy efficiency, with special emphasis on aggressive scaling of the power supply. Practical challenges will be discussed, such as early power estimation at the architectural level, power verification along the design flow, timing characterization when using dynamic voltage/frequency scaling (DVFS) and power gating with retentive sequential elements.

Instructors:
Kaushik Roy - Purdue University, West Lafayette, Indiana
Mike Keating - Synopsys, Inc., Mountain View, California
Bernard Ramanadin - STMicroelectronics, France
Matt Severson - Qualcomm CDMA Technologies Inc., San Diego, California

High-Level Synthesis for ESL Design: Fundamentals and Case Studies
Monday, July 27: 8:30 a.m. - 4:30 p.m.

Attendees participating in this tutorial will learn about High-Level Synthesis techniques they can use immediately. They will also examine the use and impact of High-Level Synthesis on the design process, from conception through implementation. At the conclusion of the tutorial, attendees also will have gained insight into the long-term direction the industry will take.

Instructors:
Daniel Gajski - University of California, Irvine, California
Jason Cong - University of California, Los Angeles, California
Nitin Chawla - STMicroelectronics, Greater Noida, India
Sumio Morioka - NEC Corp., Kawasaki, Japan
Rodric Rabbah - IBM Corp., Hawthorne, N.Y.
Scott Mahlke - University of Michigan, Ann Arbor, Michigan

Post-Silicon Validation and Runtime Verification: Ensuring Correctness after First Silicon
Friday, July 31: 9 a.m. - 5 p.m.

This tutorial will address state-of-the-art methods for detecting and correcting bugs after the first few silicon prototypes of a design become available. It is intended for microprocessor architects and designers, verification engineers, and CAD professionals interested in a better understanding of current post-silicon validation technologies. It will also benefit designers and verification experts in providing an overview of run time verification solutions that have recently been proposed by the research community.

Instructors:
Valeria Bertacco - University of Michigan, Ann Arbor, Michigan
Rand Gray - Intel Corp., Hillsboro, Oregon
Jai Kumar - Sun Microsystems, Inc., Santa Clara, California
Albert Meixner - NVIDIA Corp., Santa Clara, California
Bart Vermeulen - NXP Semiconductors, Eindhoven, The Netherlands