This column originally appeared in the December 2012 issue of The PCB Design Magazine.
Few designers ever venture to the shops that will or might build their boards, even when those manufacturers are practically next door. Even one hour spent watching fabrication processes firsthand could avoid stalling some future project for weeks while the design is re-spun to account for actual manufacturing tolerances.
In this inaugural column, I’ll dwell on the mismatch between design rules and process limits, because the shops that specialize in building complex prototypes encounter these issues day in and day out.
If you anticipate that you’ll never layout boards with more than two layers, or holes, traces and spaces smaller than 10 mils, and you’re sure you’ll never have to deal with impedance control, you have no reason other than curiosity to investigate how your boards are constructed. But if you take your job seriously, especially if you may one day route a circuit involving a BGA with a pin pitch tighter than 0.5 mm or one with 1,000 pins, and certainly if you must control impedance, it is imperative that you grasp the accuracy of the electrochemical, thermal, and mechanical operations at your current or prospective manufacturer, as well as the true stability of materials, to understand how excursions from nominal values within tolerance can accumulate and kill a design. I’m tempted to mention ivory towers, but you get the picture.
Inexperienced designers often misconstrue as ironclad the dimensions manufacturers list on their websites. For example, manufacturers – including my facility – may state that they’re capable of producing traces as fine as 2 mils wide on 2-mil spacing. I don’t doubt most of them can, but only under very limited circumstances, namely, only on an inner layer when plating isn’t involved (and absolutely not in buildup layers with buried vias). The problem isn’t the 2-mil traces: It’s the spacing.
You want 2-mil traces on 10-mil or 3-mil spacing? OK. But don’t expect less than plus or minus 25% variation along a 2-mil space no matter the distance. This obviously rules out controlling the impedance of a differential pair of those dimensions.
You might not lose sleep over tolerances for dielectric thickness, but Z-axis variation within the boundaries of a material spec compounds the challenge manufacturers face to meet impedance requirements in HDI projects, when the dielectric height driving a customer’s architecture doesn’t jibe with the blind-hole size in the design to permit a 1:1 or .75:1 via aspect ratio.
There’s no way to fudge the microvia aspect ratio. So, if a design is based on a 6-mil dielectric, but uses 4-mil vias with 8-mil pads, and the via locations and trace spacing are too tight to enlarge the pads and therefore the vias, the only way the board can be built is by decreasing the dielectric height. However, if impedance must be held to 50 ohms for traces on the top or 100 ohms for differential traces, and the dielectric height needs to be decreased by half to salvage the layout, then the trace widths and spacing must be reduced by half.
Ten percent above or below nominal thickness holds true for dielectrics down to .031” cores, but with a 6-mil core, for example, the tolerance is plus or minus 1 mil. Decreasing the dielectric thickness by half would consequently throw impedance control out the window, and narrowing the trace width and spacing by half most likely would as well. Manufacturers can adjust processes only so far to compensate for imbalanced designs. When you consider transmission line effects, there’s an optimum combination of rules that must be in place to guide the layout. A certain dielectric drives a certain minimum via size, which dictates a certain pad size, which determines trace width and therefore spacing.